module display (
    input clk,
    input rst,
    input [31:0] data,
    input [7:0] en,
    output reg [7:0] seg,
    output reg [2:0] sel
);

  always @(negedge clk or negedge rst) begin
    if (!rst) begin
      sel <= 3'd0;
    end else begin
      sel <= sel + 3'd1;
    end
  end

  reg [3:0] num;

  always @(*) begin
    case (sel)
      3'b000:  num = data[31:28];
      3'b001:  num = data[27:24];
      3'b010:  num = data[23:20];
      3'b011:  num = data[19:16];
      3'b100:  num = data[15:12];
      3'b101:  num = data[11:8];
      3'b110:  num = data[7:4];
      3'b111:  num = data[3:0];
      default: num = 4'dx;
    endcase
  end

  always @(*) begin
    if (en[sel]) begin
      case (num)
        4'h0: seg = 8'b00111111;  //"0"
        4'h1: seg = 8'b00000110;  //"1"
        4'h2: seg = 8'b01011011;  //"2"
        4'h3: seg = 8'b01001111;  //"3"
        4'h4: seg = 8'b01100110;  //"4"
        4'h5: seg = 8'b01101101;  //"5"
        4'h6: seg = 8'b01111101;  //"6"
        4'h7: seg = 8'b00000111;  //"7"
        4'h8: seg = 8'b01111111;  //"8"
        4'h9: seg = 8'b01101111;  //"9"
        4'hA: seg = 8'b01110111;  //"A"
        4'hB: seg = 8'b01111100;  //"b"
        4'hC: seg = 8'b00111001;  //"c"
        4'hD: seg = 8'b01011110;  //"d"
        4'hE: seg = 8'b01111001;  //"E"
        4'hF: seg = 8'b01110001;  //"F"
        default: seg = 8'b00000000;  //"dark"
      endcase
    end else begin
      seg = 8'b00000000;  //"dark"
    end
  end

endmodule
